ASIC Design and Synthesis, 1st ed. 2021 RTL Design Using Verilog

Langue : Anglais

Auteur : Taraate Vaibbhav

Couverture de l’ouvrage ASIC Design and Synthesis

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This book describes simple to complex ASIC design practical scenarios using Verilog. It builds a story from the basic fundamentals of ASIC designs to advanced RTL design concepts using Verilog. Looking at current trends of miniaturization, the contents provide practical information on the issues in ASIC design and synthesis using Synopsys DC and their solution. The book explains how to write efficient RTL using Verilog and how to improve design performance. It also covers architecture design strategies, multiple clock domain designs, low-power design techniques, DFT, pre-layout STA and the overall ASIC design flow with case studies. The contents of this book will be useful to practicing hardware engineers, students, and hobbyists looking to learn about ASIC design and synthesis.

Chapter 1. Introduction.- Chapter 2. Design using CMOS.- Chapter 3. ASIC design synthesis for combinational design (RTL using VHDL).- Chapter 4. ASIC Design and synthesis of complex combinational logic (RTL using VHDL).- Chapter 5. ASIC Design and synthesis of sequential logic (RTL using VHDL).- Chapter 6. ASIC design guidelines.- Chapter 7. ASIC RTL Verification.- Chapter 8. FSM using VHDL and synthesis.- Chapter 9. ASIC design improvement techniques.- Chapter 10. ASIC Synthesis using Synopsys DC.- Chapter 11. Design for Testability.- Chapter 12. Static timing analysis.- Chapter 13. Multiple Clock domain designs.- Chapter 14. Low power ASIC design.- Chapter 15. ASIC Physical design.

Vaibbhav Taraate is an entrepreneur and mentor at “1 Rupee S T”. He holds B.E. (Electronics) degree from Shivaji University, Kolhapur (1995) and received a Gold Medal for standing first in all engineering branches. He completed his M.Tech. (Aerospace Control and Guidance) at the Indian Institute of Technology (IIT) Bombay, India, in 1999. He has over 18 years of experience in semi-custom ASIC and FPGA design, primarily using HDL languages such as Verilog , VHDL and SystemVerilog. He has worked with multinational corporations as a consultant, senior design engineer, and technical manager. His areas of expertise include RTL design using VHDL, RTL design using Verilog, complex FPGA-based design, low power design, synthesis and optimization, static timing analysis, system design using microprocessors, high-speed VLSI designs, and architecture design of complex SOCs.

Unique to interpretation of ASIC design using Verilog Practical ASIC design scenarios and issues and helpful to professionals More than 150 practical examples for ASIC design, Synthesis and timing analysis Key case studies in the generic form and design synthesis and timing closure for ASIC