SystemVerilog for Hardware Description, 1st ed. 2020 RTL Design and Verification

Chapter 1: Introduction to FPGA design.- Chapter 2: Introduction to HDL.- Chapter 3:Introduction to SystemVerilog.- Chapter 4: Programming using SystemVerilog.- Chapter 5:Combinational design using SystemVerilog.- Chapter 6: Sequential design using SystemVerilog.- Chapter 7: RTL design using SystemVerilog.- Chapter 8: Verification using SystemVerilog.- Chapter 9: Design Implementation using FPGA.

Vaibbhav Taraate is an entrepreneur and mentor at "Semiconductor Training @ Rs. 1". He holds a B.E. (Electronics) degree from Shivaji University, Kolhapur in 1995. He completed his M.Tech. (Aerospace Control and Guidance) in 1999 from IIT Bombay. He has over 18 years of experience in semi-custom ASIC and FPGA design, primarily using HDL languages such as Verilog and VHDL. He has worked with few multinational corporations as a consultant, senior design engineer, and technical manager. His areas of expertise include RTL design using VHDL, RTL design using Verilog, complex FPGA-based design, low power design, synthesis/optimization, static timing analysis, system design using microprocessors, high speed VLSI designs, and architecture design of complex SOCs.