From Contamination to Defects, Faults and Yield Loss, 1996 Simulation and Applications Frontiers in Electronic Testing Series, Vol. 5
Modern VLSI research and engineering (which includes design manufacturing and testing) encompasses a very broad range of disciplines such as chemistry, physics, material science, circuit design, mathematics and computer science. Due to this diversity, the VLSI arena has become fractured into a number of separate sub-domains with little or no interaction between them. This is the case with the relationships between testing and manufacturing.
From Contamination to Defects, Faults and Yield Loss: Simulation andApplications focuses on the core of the interface between manufacturing and testing, i.e., the contamination-defect-fault relationship. The understanding of this relationship can lead to better solutions of many manufacturing and testing problems.
Failure mechanism models are developed and presented which can be used to accurately estimate probability of different failures for a given IC. This information is critical in solving key yield-related applications such as failure analysis, fault modeling and design manufacturing.
Date de parution : 09-2011
Ouvrage de 150 p.
15.5x23.5 cm
Disponible chez l'éditeur (délai d'approvisionnement : 15 jours).
Prix indicatif 105,49 €
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Mots-clés :
CMOS; VLSI; circuit design; computer; integrated circuit; manufacturing; material; mechanism; model; modeling; physics; simulation; testing; transistor