Sustainable Wireless Network-on-Chip Architectures
Auteurs : Murray Jacob, Wettin Paul, Pande Partha Pratim, Shirazi Behrooz
Sustainable Wireless Network-on-Chip Architectures focuses on developing novel Dynamic Thermal Management (DTM) and Dynamic Voltage and Frequency Scaling (DVFS) algorithms that exploit the advantages inherent in WiNoC architectures. The methodologies proposed?combined with extensive experimental validation?collectively represent efforts to create a sustainable NoC architecture for future many-core chips. Current research trends show a necessary paradigm shift towards green and sustainable computing. As implementing massively parallel energy-efficient CPUs and reducing resource consumption become standard, and their speed and power continuously increase, energy issues become a significant concern.
The need for promoting research in sustainable computing is imperative. As hundreds of cores are integrated in a single chip, designing effective packages for dissipating maximum heat is infeasible. Moreover, technology scaling is pushing the limits of affordable cooling, thereby requiring suitable design techniques to reduce peak temperatures. Addressing thermal concerns at different design stages is critical to the success of future generation systems. DTM and DVFS appear as solutions to avoid high spatial and temporal temperature variations among NoC components, and thereby mitigate local network hotspots.
1. Introduction 2. Current Research Trends and State-of-the-Art NoC Designs3. Complex Network Inspired NoC Architecture4. Wireless Small-World NoCs5. Topology Agnostic Routing for Irregular Networks6. Performance Evaluation and Design Tradeoffs of Wireless SWNoCs7. Dynamic Voltage and Frequency Scaling 8. Dynamic Thermal Management9. Joint DTM and DVFS Techniques10. Conclusions and Possible Future Explorations
Paul Wettin received his PhD in Electrical and Computer Engineering at the School of Electrical Engineering and Computer Science, Washington State University in 2014 and received his BS in Computer Engineering at Washington State University in 2010. He is a Senior ASIC Design Engineer at Marvell Semiconductor Inc., Boise. His current research interests include wireless Network-on-Chip architectures, specifically low-power architectures that use DVFS and DTM techniques to reduce chip temperature. He is a member of Tau Beta Pi, the national engineering honors society, and a member of the IEEE.
Partha Pratim Pande received the M.S. degree in computer science from the National University of Singapore and the Ph.D. degree in electrical and computer engineering from the University of British Columbia, Vancouver, BC, Canada. He is an Associate Professor at the School of Electrical Engineering and Computer Science, Washington State University, Pullman. His current research interests are novel interconnect architectures for multicore chips, on-chip wireless communication networks, and hardwar
- Defines new complex, sustainable network-on-chip architectures to reduce network latency and energy
- Develops topology-agnostic dynamic thermal management and dynamic voltage and frequency scaling techniques
- Describes joint strategies for network- and core-level sustainability
- Discusses novel algorithms that exploit the advantages inherent in Wireless Network-on-Chip architectures
Date de parution : 03-2016
Ouvrage de 162 p.
15x22.8 cm
