Sequential Logic and Verilog HDL Fundamentals
Auteur : Cavanagh Joseph
Sequential Logic and Verilog HDL Fundamentals discusses the analysis and synthesis of synchronous and asynchronous sequential machines. These machines are implemented using Verilog Hardware Description Language (HDL), in accordance with the Institute of Electrical and Electronics Engineers (IEEE) Standard: 1364-1995.
The book concentrates on sequential logic design with a focus on the design of various Verilog HDL projects.Emphasis is placed on structured and rigorous design principles that can be applied to practical applications. Each step of the analysis and synthesis procedures is clearly delineated. Each method that is presented is expounded in sufficient detail with accompanying examples. Many analysis and synthesis examples use mixed-logic symbols incorporating both positive- and negative-input logic gates for NAND (not AND) and NOR (not OR) logic, while other examples utilize only positive-input logic gates. The use of mixed logic parallels the use of these symbols in the industry.
The bookis intended to be a tutorial, and as such, is comprehensive and self-contained. All designs are carried through to completion?nothing is left unfinished or partially designed. Each chapter contains numerous problems of varying complexity to be designed by the reader using Verilog HDL design techniques. The Verilog HDL designs include the design module, the test bench module that tests the design for correct functionality, the outputs obtained from the test bench, and the waveforms obtained from the test bench.
Sequential Logic and Verilog HDL Fundamentals presents Verilog HDL with numerous design examples to help the reader thoroughly understand this popular hardware description language. The book is designed for practicing electrical engineers, computer engineers, and computer scientists; for graduate students in electrical engineering, computer engineering, and computer science; and for senior-level undergraduate students.
Introduction to Verilog HDL. Synthesis of Synchronous Sequential Machines 1 Using Verilog HDL. Synthesis of Synchronous Sequential Machines 2 Using Verilog HDL. Synthesis of Asynchronous Sequential Machines Using Verilog HDL. Synthesis of Pulse-Mode Asynchronous Sequential Machines Using Verilog HDL. Appendices.
Joseph Cavanagh is an adjunct professor in the Computer Engineering Department at Santa Clara University, California, USA. He is the author of several textbooks, including Computer Arithmetic and Verilog HDL Fundamentals (2009), Digital Design and Verilog HDL Fundamentals (2008), Verilog HDL: Digital Design and Modeling (2007), and Sequential Logic: Analysis and Synthesis (2006), as well as a novel, The Computer Conspiracy.
Date de parution : 10-2015
17.8x25.4 cm
Disponible chez l'éditeur (délai d'approvisionnement : 15 jours).
Prix indicatif 208,65 €
Ajouter au panierThèmes de Sequential Logic and Verilog HDL Fundamentals :
Mots-clés :
Test Bench Module; Verilog Hardware Description Language; Structural Design Module; Sequential Logic; Mealy Machine; IEEE Standard: 1364-1995; Continuous Assignment Statement; Institute of Electrical and Electronics Engineers Standard: 1364-1995; Moore Machine; Pulse-Mode Asynchronous Sequential Machines; Behavioral Design Module; Asynchronous Sequential Machines; Synchronous Sequential Machines; Representative Timing Diagram; Sequential Machine Synthesis; Dataflow Modeling; Sequential Machine Analysis; Nonlinear Select Multiplexer; Verilog HDL; Minterm Location; Asynchronous Sequential Machine; Pulse Mode Asynchronous Sequential Machine; Primitive Flow Table; Merged Flow Table; Moore Pulse Mode Asynchronous Sequential Machine; Moore Pulse Mode; Pulse Mode Machine; Mealy Pulse Mode Asynchronous Sequential Machine; Mealy Pulse Mode; Modulo-10 Counter; SR Latch; Pal Device; Excitation Map; Karnaugh Map