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Reconfigurable Computing Systems Engineering Virtualization of Computing Architecture

Langue : Anglais

Auteur :

Couverture de l’ouvrage Reconfigurable Computing Systems Engineering

Reconfigurable Computing Systems Engineering: Virtualization of Computing Architecture describes the organization of reconfigurable computing system (RCS) architecture and discusses the pros and cons of different RCS architecture implementations. Providing a solid understanding of RCS technology and where it?s most effective, this book:

  • Details the architecture organization of RCS platforms for application-specific workloads
  • Covers the process of the architectural synthesis of hardware components for system-on-chip (SoC) for the RCS
  • Explores the virtualization of RCS architecture from the system and on-chip levels
  • Presents methodologies for RCS architecture run-time integration according to mode of operation and rapid adaptation to changes of multi-parametric constraints
  • Includes illustrative examples, case studies, homework problems, and references to important literature

A solutions manual is available with qualifying course adoption.

Reconfigurable Computing Systems Engineering: Virtualization of Computing Architecture offers a complete road map to the synthesis of RCS architecture, exposing hardware design engineers, system architects, and students specializing in designing FPGA-based embedded systems to novel concepts in RCS architecture organization and virtualization.

Introduction to Reconfigurable Computing Systems. Organization of the Field of Configurable Resources. Architecture of the On-Chip Processing Elements. Reconfigurable Communication Infrastructure in the FCR. System-Level Organization of the FCR. Configuration Memory and Architecture Virtualization in RCS. Reconfiguration Process Organization in the On-Chip Level of a Reconfigurable Computing System. RCS Architecture Configuration and Runtime Reconfiguration. Virtualization of the Architectural Components of a System on Chip. Virtualization of Reconfigurable Computing System Architecture.

Academic and Professional Practice & Development

Lev Kirischian, Ph.D, P.Eng, Member IEEE, has been affiliated with Ryerson University, Canada for 18 years. His research involves dynamically reconfigurable computing systems, automated architectural synthesis of data-stream processors, and workload-adaptive and self-healing reconfigurable architectures. He participated in the research and development of the first-generation Soviet supercomputers with reconfigurable architectures in the 1980s, FPGA-based segment of COFDM modulation technology for digital audio/video broadcasting systems for satellite and terrestrial networks (used in the SiriusXM satellite radio network), workload adaptive and self-restorable space-borne embedded computer platforms, and 3D-panoramic machine vision systems, among other technologies. In the last decade, he has developed and taught several courses associated with high-performance and reconfigurable computing as well as high-level synthesis of application-specific processors.

Date de parution :

15.6x23.4 cm

Disponible chez l'éditeur (délai d'approvisionnement : 14 jours).

60,02 €

Ajouter au panier

Date de parution :

15.6x23.4 cm

Disponible chez l'éditeur (délai d'approvisionnement : 15 jours).

148,11 €

Ajouter au panier

Thèmes de Reconfigurable Computing Systems Engineering :

Mots-clés :

FPGA Device; RCS; Runtime Reconfigurable Computing System; Configuration Memory; Dynamically Reconfigurable Computing System; PR; Reconfigurable Computing System PCB Layout; Data Execution Process; Reconfigurable Computing System Printed Circuit Board Layout; Partial Dynamic Reconfiguration; Reconfigurable Computing System Application; Task Segments; Reconfigurable Computing System Example; Power Consumption; Reconfigurable Computing System Case Studies; Reconfiguration Time; Reconfigurable Computing System Design; Configuration Cache; Reconfigurable Computing System Verification; Execution Time; Reconfigurable Computing System Prototyping; Configuration Memory Cells; Reconfigurable Computing System Implementation; Cycle Time; Virtual Computing; RISC Processor; Virtual Computing Architecture; Configuration Bus; Rapid Multi-Parametric Optimization; Hardware Overhead; Reconfigurable Computing System Optimization; Configurable Logic Blocks; Reconfigurable Computing System Synthesis; Configuration Port; Reconfigurable Computing System Virtualization; Task Algorithm; Reconfigurable Computing System Development; Runtime Reconfiguration; Virtual Processor; Configuration Frames; Virtual Hardware; Xilinx Virtex-6 FPGA; Virtual Component; Functional Segment; IP Core; Daisy Chain Configuration; Reconfigurable Computing System on Chip; Configuration Scheme; Reconfigurable Computing System Component; Reconfigurable Computing System Hardware; Reconfigurable Computing System Architecture; Reconfigurable Computing System Organization; Reconfigurable Computing System Platform; Reconfigurable Computing System; Intellectual Property Block; IP Block; Intellectual Property Core; Field Programmable Gate Array; FPGA; Reconfigurable Computing System Engineering; Rapid Adaptation to Multi-Parametric Constraints; System on Programmable Chip; SoPC; System on Chip; SoC; Temporal Partitioning Mechanism; Spatial Partitioning Mechanism