Computer Organization and Design RISC-V Edition (2nd Ed.) The Hardware Software Interface The Morgan Kaufmann Series in Computer Architecture and Design Series
Auteurs : Patterson David A., Hennessy John L.
1. Computer Abstractions and Technology 2. Instructions: Language of the Computer 3. Arithmetic for Computers 4. The RISC-V Processor 5. Large and Fast: Exploiting Memory Hierarchy 6. Parallel Processors from Client to Cloud
Appendix A. The Basics of Logic Design B. Graphics and Computing GPUs C. Mapping Control to Hardware D. A Survey of RISC Architectures
ACM named John L. Hennessy a recipient of the 2017 ACM A.M. Turing Award for pioneering a systematic, quantitative approach to the design and evaluation of computer architectures with enduring impact on the microprocessor industry. John L. Hennessy is a Professor of Electrical Engineering and Computer Science at Stanford University, where he has been a member of the faculty since 1977 and was, from 2000 to 2016, its tenth President. Prof. Hennessy is a Fellow of the IEEE and ACM; a member of the National Academy of Engineering, the National Academy of Science, and the American Philosophical Society; and a Fellow of the American Academy of Arts and Sciences. Among his many awards are the 2001 Eckert-Mauchly Award for his contributions to RISC techn
- Covers parallelism in-depth, with examples and content highlighting parallel hardware and software topics
- Focuses on 64-bit address, ISA to 32-bit address, and ISA for RISC-V because 32-bit RISC-V ISA is simpler to explain, and 32-bit address computers are still best for applications like embedded computing and IoT
- Includes new sections in each chapter on Domain Specific Architectures (DSA)
- Provides updates on all the real-world examples in the book
Date de parution : 04-2021
Ouvrage de 736 p.
19x23.4 cm
Thèmes de Computer Organization and Design RISC-V Edition :
Mots-clés :
system design; processor; parallel; cloud; mobile; GPU; memory; instruction set; client; digital design; logic; operations; multiprocessor; pipelining; hardware; software; cluster; network; computer arithmetic