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Substrate noise coupling in RFICs (Analog circuits & signal processing), Softcover reprint of hardcover 1st ed. 2008 Analog Circuits and Signal Processing Series

Langue : Anglais

Auteurs :

Couverture de l’ouvrage Substrate noise coupling in RFICs (Analog circuits & signal processing)
Substrate Noise Coupling in RFICs addresses substrate noise coupling in RF and mixed signal ICs when used in a system on chip (SoC) containing digital ICs as well. This trend of integrating RF, mixed signal ICs with large digital ICs is found in many of today's commercial ICs such as single chip Wi-Fi or Bluetooth solutions and is expected to grow rapidly in the future. The book reports modeling and simulation techniques for substrate noise coupling effects in RFICs and introduces isolation structures and design guides to mitigate such effects with the ultimate goal of enhancing the yield of RF and mixed signal SoCs . This is particularly critical when process feature sizes scale down to the nano meter range. Substrate Noise Coupling in RFICs reports silicon measurements, new test and noise isolation structures as well as calibration of a design flow used in the design and debug phases of RFICs. A design guide is articulated to be used by RFIC designers to maximize signal isolation and optimize chip floor plan, power and ground domains. Industrial examples of RFICs are given as demonstration vehicles to validate the proposed techniques. Some emphasis is put on the design of on-chip spiral inductors and the impact of the substrate on their performance. To our knowledge, this is the first title devoted to the topic of substrate noise coupling in RFICs as part of a large SoC.
Chapter 1 Introduction. 1.1 Motivation and Objectives. 1.2 Contributions. 1.3 Book Organization. Chapter 2 Analysis of Substrate Noise Coupling. 2.1. Process Regions. 2.2. Process cross sections. 2.3. Connection of devices to the substrate. 2.4. Noise coupling mechanism. 2.5. Substrate doping profile tradeoffs. 2.6. Substrate Model extraction in the IC design flow. 2.7. Doping Profile Considerations. 2.8. Substrate model extraction kernels. 2.9. Conclusion. Chapter 3 Experimental Data to calibrate the design flow. 3.1. Introduction. 3.2. The test chip. 3.3. Baseline Isolation. 3.4. Effect of p-guard ring on isolation. 3.5. Effect of n-guard ring on isolation. 3.6. Effect of deep n-well on isolation. 3.7. Effect of deep trench on isolation. 3.8. De-embedding. 3.9. Conclusion. Chapter 4 Design Guide for Substrate Noise Isolation for RF Applications. 4.1. Introduction. 4.2. Isolation in Low resistivity substrate. 4.3. Isolation vs. Frequency for different isolation structures. 4.4. Effect of back plane connection on the noise isolation in high resistivity substrates. 4.5. Substrate Contacts: Front side or Backside? Both. 4.6. P+ Guard Ring Isolation. 4.7. P+ and N+ Guard Rings Isolation. 4.8. Floor planning techniques to minimize coupling. 4.9. Circuit techniques to minimize coupling. 4.10. Active guard rings. 4.11. Conclusion. Chapter 5 On Chip Inductor Design Flow. 5.1. Introduction. 5.2. Integrated Inductors. 5.3. Inductor Design Flow. 5.4. Analytical exploration of the design space. 5.5. Inductor Model and Substrate Parasitics. 5.6. Calibrating the field solver. 5.7. Model fit. 5.8. DFM effects. 5.9. Conclusion. Chapter 6 Case studies for the impact and remedy of substrate noise coupling. 6.1. Introduction. 6.2. System Level Case study. 6.3.Block Level Case study. 6.4. Device Level Case study. 6.5.Conclusion. Chapter 7 Conclusion.
Mohammed Ismail is the Springer Series Advisor for the Analog Circuits and Signal Processing book series

Addresses substrate noise coupling in RF and mixed signal ICs when used in a system on chip(SoC) containing digital ICs as well

Great reference for courses in RFIC and mixed signal ICs, and for design project courses

Reports silicon measurements, new test and noise isolation structures as well as calibration of a design flow used in the design and debug phases of RFIC circuits

The first title devoted to the topic of substrate noise coupling in RFICs as part of a large SoC

Date de parution :

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15.5x23.5 cm

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Prix indicatif 126,59 €

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Date de parution :

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