Nano-scale CMOS Analog Circuits Models and CAD Techniques for High-Level Design
Auteurs : Pandit Soumya, Mandal Chittaranjan, Patra Amit
Reliability concerns and the limitations of process technology can sometimes restrict the innovation process involved in designing nano-scale analog circuits. The success of nano-scale analog circuit design requires repeat experimentation, correct analysis of the device physics, process technology, and adequate use of the knowledge database.
Starting with the basics, Nano-Scale CMOS Analog Circuits: Models and CAD Techniques for High-Level Design introduces the essential fundamental concepts for designing analog circuits with optimal performances. This book explains the links between the physics and technology of scaled MOS transistors and the design and simulation of nano-scale analog circuits. It also explores the development of structured computer-aided design (CAD) techniques for architecture-level and circuit-level design of analog circuits.
The book outlines the general trends of technology scaling with respect to device geometry, process parameters, and supply voltage. It describes models and optimization techniques, as well as the compact modeling of scaled MOS transistors for VLSI circuit simulation.
? Includes two learning-based methods: the artificial neural network (ANN) and the least-squares support vector machine (LS-SVM) method
? Provides case studies demonstrating the practical use of these two methods
? Explores circuit sizing and specification translation tasks
? Introduces the particle swarm optimization technique and provides examples of sizing analog circuits
? Discusses the advanced effects of scaled MOS transistors like narrow width effects, and vertical and lateral channel engineering
Nano-Scale CMOS Analog Circuits: Models and CAD Techniques for High-Level Design
Introduction. High-Level Modeling and Design Techniques. Modeling of Scaled MOS Transistor for VLSI Circuit Simulation. Performance and Feasibility Model Generation using Learning based Approach. Circuit Sizing and Specification Translation. Advanced Effects of Scaled MOS Transistors. Process Variability and Reliability of Nano-scale CMOS Analog Circuits. Bibliography.
Soumya Pandit received a B.Sc degree with Physics Honors, M.Sc degree in electronic science from University of Calcutta in 1998 and 2000, and an M.Tech degree in radio physics and electronics from the same university in 2002. He obtained his PhD degree from Indian Institute of Technology, Kharagpur in information technology in the year 2009. His current research activities are on statistical CMOS analog circuit design and optimization, process-device-circuit interaction, and soft computing applications. Dr. Pandit has to his credit several international journal and conference publications. He is a member of IEEE, USA and an associate member of the Institute of Engineers (India).
Chittaranjan Mandal Amit Patra
Date de parution : 02-2014
Ouvrage de 500 p.
15.6x23.4 cm
Thèmes de Nano-scale CMOS Analog Circuits :
Mots-clés :
Spice Simulation; High-Level Modeling and Design Techniques; MOS Transistor; Performance and Feasibility Model Generation using Learning based Approach; Weak Inversion Region; Circuit Sizing and Specification Translation; Threshold Voltage; Advanced Effects of Scaled MOS Transistors; Drain Current; Process Variability and Reliability of Nano-scale CMOS Analog Circuits; Spice Simulation Result; Chittaranjan Mandal; Short Channel Effects; Amit Patra; PSO Algorithm; Interface Trap; Constant Field Scaling; Flicker Noise; Feasible Design Space; Grid Search Technique; NN Model; Scale CMOS Technology; Technology Node; Inversion Charge Density; LER; Velocity Saturation Region; Effective Channel Length; Power Consumption; Interface Trap Density; Design Space Exploration; Spiral Inductor; Drain Current Model
