Logic Synthesis and Verification, 2002 The Springer International Series in Engineering and Computer Science Series, Vol. 654
Coordonnateurs : Hassoun Soha, Sasao Tsutomu
Logic Synthesis and Verification provides a state-of-the-art view of logic synthesis and verification. It consists of fifteen chapters, each focusing on a distinct aspect. Each chapter presents key developments, outlines future challenges, and lists essential references.
Two unique features of this book are technical strength and comprehensiveness. The book chapters are written by twenty-eight recognized leaders in the field and reviewed by equally qualified experts. The topics collectively span the field.
Logic Synthesis and Verification fills a current gap in the existing CAD literature. Each chapter contains essential information to study a topic at a great depth, and to understand further developments in the field. The book is intended for seniors, graduate students, researchers, and developers of related Computer-Aided Design (CAD) tools.
From the foreword: "The commercial success of logic synthesis and verification is due in large part to the ideas of many of the authors of this book. Their innovative work contributed to design automation tools that permanently changed the course of electronic design." by Aart J. de Geus, Chairman and CEO, Synopsys, Inc.
Date de parution : 07-2013
Ouvrage de 454 p.
15.5x23.5 cm
Disponible chez l'éditeur (délai d'approvisionnement : 15 jours).
Prix indicatif 158,24 €
Ajouter au panierDate de parution : 11-2001
Ouvrage de 454 p.
15.5x23.5 cm
Thèmes de Logic Synthesis and Verification :
Mots-clés :
Analysis; CAD; algorithms; automation; computer; computer-aided design (CAD); integrated circuit; logic; optimization; verification