Hardware Verification with System Verilog, Softcover reprint of hardcover 1st ed. 2007 An Object-Oriented Framework

This is the second of our books designed to help the professional verifier manage complexity. This time, we have responded to a growing interest not only in object-oriented programming but also in SystemVerilog. The writing of this second handbook has been just another step in an ongoing masochistic endeavor to make your professional lives as painfree as possible. The authors are not special people. We have worked in several companies, large and small, made mistakes, and generally muddled through our work. There are many people in the industry who are smarter than we are, and many coworkers who are more experienced. However, we have a strong desire to help. We have been in the lab when we bring up the chips fresh from the fab, with customers and sales breathing down our necks. We?ve been through software 1 bring-up and worked on drivers that had to work around bugs in production chips. What we feel makes us unique is our combined broad experience from both the software and hardware worlds. Mike has over 20 years of experience from the software world that he applies in this book to hardware verification. Robert has over 12 years of experience with hardware verification, with a focus on environments and methodology.

SystemVerilog and Verification (The Why and How).- Why SystemVerilog?.- OOP and SystemVerilog.- A Layered Approach.- An Open-Source Environment with SystemVerilog.- Teal Basics.- Truss: A Standard Verification Framework.- Truss Flow.- Truss Example.- Using OOP for Verification (Best Practices).- Thinking OOP.- Designing with OOP.- OOP Classes.- OOP Connections.- Coding OOP.- Examples (Putting It All Together).- Block-Level Testing.- Chip-Level Testing.- Things to Remember.- Examples (Putting It All Together).

Focuses on Object Orientation Programming and its applications for C++ and SystemVerilog Includes open source verification framework and examples Provides explanations as to why and when certain features should be used with the SystemVerilog language and syntax