Top-Down Digital VLSI Design From Architectures to Gate-Level Circuits and FPGAs
Auteur : Kaeslin Hubert
Top-Down VLSI Design: From Architectures to Gate-Level Circuits and FPGAs represents a unique approach to learning digital design. Developed from more than 20 years teaching circuit design, Doctor Kaeslin?s approach follows the natural VLSI design flow and makes circuit design accessible for professionals with a background in systems engineering or digital signal processing. It begins with hardware architecture and promotes a system-level view, first considering the type of intended application and letting that guide your design choices.
Doctor Kaeslin presents modern considerations for handling circuit complexity, throughput, and energy efficiency while preserving functionality. The book focuses on application-specific integrated circuits (ASICs), which along with FPGAs are increasingly used to develop products with applications in telecommunications, IT security, biomedical, automotive, and computer vision industries. Topics include field-programmable logic, algorithms, verification, modeling hardware, synchronous clocking, and more.
1. Introduction to Microelectronics 2. Field Programmable Logic 3. From Algorithms to Architectures 4. Circuit Modeling with Hardware Description Languages5. Functional Verification6. The Case for Synchronous Design7. Clocking of Synchronous Circuits 8. Acquisition of Asynchronous Data A. Elementary Digital Electronics B. Finite State Machines
Students in upper undergraduate or graduate courses on studying VLSI and microelectronics, professional system engineers working in these areas
- Demonstrates a top-down approach to digital VLSI design.
- Provides a systematic overview of architecture optimization techniques.
- Features a chapter on field-programmable logic devices, their technologies and architectures.
- Includes checklists, hints, and warnings for various design situations.
- Emphasizes design flows that do not overlook important action items and which include alternative options when planning the development of microelectronic circuits.
Date de parution : 12-2014
Ouvrage de 598 p.
19x23.3 cm