The Interaction of Compilation Technology and Computer Architecture, Softcover reprint of the original 1st ed. 1994

In brief summary, the following results were presented in this work: ? A linear time approach was developed to find register requirements for any specified CS schedule or filled MRT. ? An algorithm was developed for finding register requirements for any kernel that has a dependence graph that is acyclic and has no data reuse on machines with depth independent instruction templates. ? We presented an efficient method of estimating register requirements as a function of pipeline depth. ? We developed a technique for efficiently finding bounds on register require­ ments as a function of pipeline depth. ? Presented experimental data to verify these new techniques. ? discussed some interesting design points for register file size on a number of different architectures. REFERENCES [1] Robert P. Colwell, Robert P. Nix, John J O'Donnell, David B Papworth, and Paul K. Rodman. A VLIW Architecture for a Trace Scheduling Com­ piler. In Architectural Support for Programming Languages and Operating Systems, pages 180-192, 1982. [2] C. Eisenbeis, W. Jalby, and A. Lichnewsky. Compile-Time Optimization of Memory and Register Usage on the Cray-2. In Proceedings of the Second Workshop on Languages and Compilers, Urbana l/inois, August 1989. [3] C. Eisenbeis, William Jalby, and Alain Lichnewsky. Squeezing More CPU Performance Out of a Cray-2 by Vector Block Scheduling. In Proceedings of Supercomputing '88, pages 237-246, 1988. [4] Michael J. Flynn. Very High-Speed Computing Systems. Proceedings of the IEEE, 54:1901-1909, December 1966.

1. Introduction and Overview; D.J. Lilja, P.L. Bird, R.Y. Kain. 2. Architectural Support for Compile-Time Speculation; M.D. Smith. 3. Register Requirements for High Performance Code Scheduling; B. Mangione-Smith. 4. Data Dependencies in Decoupled Pipelined Loops; P.L. Bird. 5. The Effects of Traditional Compiler Optimization on Superscalar Architectural Design; T.M. Conte, K.N.P. Menezes. 6. Dynamic Program Monitoring and Transformation Using the OMOS Object Server; D.B. Orr, R.W. Mecklenburg, P.J. Hoogenboom, J. Lepreau. 7. Performance Limits of Compiler-Directed Multiprocessor Cache Coherence Enforcement; F. Mounes-Toussi, D.J. Lilja. 8. Compiling HPF for Distributed Memory MIMD Computers; Z. Bozkus, A. Choudhary, G. Fox, T. Haupt, S. Tanka. 9. The Influence of the Object-Oriented Language Model on a Supporting Architecture; M. Wolczko, I. Williams. 10. Project Triton: Towards Improved Programmability of Parallel Computers; M. Philippsen, T.M. Warschko, W.F. Tichy, C.G. Herter, E.A. Heinz, P. Lukowicz. Index.

This book demonstrates the importance of integrating contemporary compilation technology with a supporting computer architecture to enhance system performance. Each chapter examines how best to exploit the interaction between the architecture and the compiler. The book explores three different aspects of this interaction. Chapters 2-6 examine the interaction of the compiler and the architecture at the instruction level on uniprocessors with multiple function units and highly segmented pipelines. Chapters 7 and 8 examine compilation issues for multiprocessor systems. The last two chapters discuss how programming language features can influence the design of both uniprocessor and multiprocessor systems.