Network-on-Chip Architectures, 2010 A Holistic Design Exploration Lecture Notes in Electrical Engineering Series, Vol. 45

[2]. The Cell Processor from Sony, Toshiba and IBM (STI) [3], and the Sun UltraSPARC T1 (formerly codenamed Niagara) [4] signal the growing popularity of such systems. Furthermore, Intel?s very recently announced 80-core TeraFLOP chip [5] exemplifies the irreversible march toward many-core systems with tens or even hundreds of processing elements. 1.2 The Dawn of the Communication-Centric Revolution The multi-core thrust has ushered the gradual displacement of the computati- centric design model by a more communication-centric approach [6]. The large, sophisticated monolithic modules are giving way to several smaller, simpler p- cessing elements working in tandem. This trend has led to a surge in the popularity of multi-core systems, which typically manifest themselves in two distinct incarnations: heterogeneous Multi-Processor Systems-on-Chip (MPSoC) and homogeneous Chip Multi-Processors (CMP). The SoC philosophy revolves around the technique of Platform-Based Design (PBD) [7], which advocates the reuse of Intellectual Property (IP) cores in flexible design templates that can be customized accordingly to satisfy the demands of particular implementations. The appeal of such a modular approach lies in the substantially reduced Time-To- Market (TTM) incubation period, which is a direct outcome of lower circuit complexity and reduced design effort. The whole system can now be viewed as a diverse collection of pre-existing IP components integrated on a single die.

Abstract. Acknowledgments. 1. Introduction. 2. A Baseline NoC Architecture Part I MICRO-Architectural Exploratioin 3. ViChaR: A Dynamic Virtual Channel Regulator for NoC Routers. 4. RoCo: The Row-Column Decoupled Router. 5. Exploring Fault-Tolerant Network-on-Chip Architectures. 6. On the Effects of Process Variation in Network-on-Chip Architectures. Part II MACRO-Architectural Exploration 7. The Quest for Scalable On-Chip Interconnection Networks. 8. Design and Management of 3D Chip Multiprocessors Using Network-In-Memory (NetInMem). 9. A Novel Dimensionally-Decomposed Router for On-Chip Communication in 3D Architectures. 10. Digest of Additional NoC MACRO-Architectural Research. 11. Conclusions & Future Work. References.