Multiscalar Processors, 2003 The Springer International Series in Engineering and Computer Science Series, Vol. 718

Multiscalar Processors presents a comprehensive treatment of the basic principles of Multiscalar execution, and advanced techniques for implementing the Multiscalar concepts. Special emphasis is placed on highlighting the major challenges involved in Multiscalar processing. This book is organized into nine chapters, and provides an excellent synopsis of a large body of research carried out on multiscalar processors in the last decade. It starts with technology trends that provide an impetus to the development of multiscalar processors and shape the development of future processors. The work ends with a review of the recent developments related to multiscalar processors.

1 Introduction.- 1.1 Technology Trends.- 1.2 Instruction-Level Parallelism (ILP).- 1.3 Thread-Level Parallelism (TLP).- 1.4 The Multiscalar Paradigm.- 1.5 The Multiscalar Story.- 1.6 The Rest of the Story.- 2 The Multiscalar Paradigm.- 2.1 Ideal TLP Processing Paradigm—The Goal.- 2.2 Multiscalar Paradigm—The Basic Idea.- 2.3 Multiscalar Execution Example.- 2.4Interesting Aspects of the Multiscalar Paradigm.- 2.5Comparison with Other Processing Paradigms.- 2.6 The Multiscalar Processor.- 2.7 Summary.- 3 Multiscalar Threads—Static Aspects.- 3.1 Structural Aspects of Multiscalar Threads.- 3.2. Data Flow Aspects of Multiscalar Threads.- 3.3 Program Partitioning.- 3.4.Static Thread Descriptor.- 3.5.Concluding Remarks.- 4 Multiscalar Threads—Dynamic Aspects.- 4.1. Multiscalar Microarchitecture.- 4.2. Thread Processing Phases.- 4.3 Thread Assignment Policies.- 4.4 Thread Execution Policies.- 4.5 Recovery Policies.- 4.6 Exception Handling.- 4.7 Concluding Remarks.- 5 Multiscalar Processor—Control Flow.- 5.1 Inter-Thread Control Flow Predictor.- 5.2 Intra-Thread Branch Prediction.- 5.3 Intra-Thread Return Address Prediction.- 5.4 Instruction Supply.- 5.5 Concluding Remarks.- 6 Multiscalar Processor—Register Data Flow.- 6.1 Nature of Register Data Flow in a Multiscalar Processor.- 6.2 Multi-Version Register File—Basic Idea.- 6.3 Inter-Thread Synchronization: Busy Bits.- 6.4 Multi-Version Register File—Detailed Operation.- 6.5 Data Speculation: Relaxing Inter-Thread Synchronization.- 6.6 Compiler and ISA Support.- 6.7 Concluding Remarks.- 7 Multiscalar Processor—Memory Data Flow.- 7.1 Nature of Memory Data Flow in a Multiscalar Processor.- 7.2 Address Resolution Buffer (ARB).- 7.3 Multi-Version Cache.- 7.4 Speculative Version Cache.- 7.5 Concluding Remarks.- 8Multiscalar Compilation.- 8.1 Role of the Compiler.- 8.2 Program Partitioning Criteria.- 8.3 Program Partitioning Heuristics.- 8.4 Implementation of Program Partitioning.- 8.5 Intra-Thread Static Scheduling.- 8.6 Concluding Remarks.- 9 Recent Developments.- 9.1 Incorporating Fault Tolerance.- 9.2 Multiscalar Processor with Trace-based Threads.- 9.3 Hierarchical Multiscalar Processor.- 9.4 Compiler-Directed Thread Execution.- 9.5 A Commercial Implementation: NEC Merlot.