Lavoisier S.A.S.
14 rue de Provigny
94236 Cachan cedex
FRANCE

Heures d'ouverture 08h30-12h30/13h30-17h30
Tél.: +33 (0)1 47 40 67 00
Fax: +33 (0)1 47 40 67 02


Url canonique : www.lavoisier.fr/livre/autre/modeling-verification-and-exploration-of-task-level-concurrency-in-real-time-embedded-systems/thoen/descriptif_1600668
Url courte ou permalien : www.lavoisier.fr/livre/notice.asp?ouvrage=1600668

Modeling, Verification and Exploration of Task-Level Concurrency in Real-Time Embedded Systems, Softcover reprint of the original 1st ed. 2000

Langue : Anglais

Auteurs :

Couverture de l’ouvrage Modeling, Verification and Exploration of Task-Level Concurrency in Real-Time Embedded Systems
system is a complex object containing a significant percentage of elec­ A tronics that interacts with the Real World (physical environments, humans, etc. ) through sensing and actuating devices. A system is heterogeneous, i. e. , is characterized by the co-existence of a large number of components of disparate type and function (for example, programmable components such as micro­ processors and Digital Signal Processors (DSPs), analog components such as AID and D/A converters, sensors, transmitters and receivers). Any approach to system design today must include software concerns to be viable. In fact, it is now common knowledge that more than 70% of the development cost for complex systems such as automotive electronics and communication systems are due to software development. In addition, this percentage is increasing constantly. It has been my take for years that the so-called hardware-software co-design problem is formulated at a too low level to yield significant results in shorten­ ing design time to the point needed for next generation electronic devices and systems. The level of abstraction has to be raised to the Architecture-Function co-design problem, where Function refers to the operations that the system is supposed to carry out and Architecture is the set of supporting components for that functionality. The supporting components as we said above are heteroge­ neous and contain almost always programmable components.
1. Introduction.- 1. Systems-on-a-chip.- 2. Heterogeneous real-time embedded systems.- 3. Unified meta design flow for multi-media and telecom applications.- 4. Design methodology & CAD design support.- 5. Overview of the book.- 2. Related Work and Contemporary Approaches.- 1. Manual approach.- 2. Real-time operating systems.- 3. Processor architecture integration.- 4. Task concurrency management.- 5. Motivation for a new approach.- 3. System Representation Model.- 1. Model requirements.- 2. Related Work — Models considering time.- 3. Basic Multi-Thread Graph model.- 4. MTG model extended with data communication.- 5. MTG model extended with timing.- 6. MTG model extended with hierarchy.- 7. Miscellaneous extensions.- 8. Advantages of the MTG model.- 9. Future extensions.- 10. Summary.- 4. Timing Analysis.- 1. Problem formulation.- 2. Related work — Timing verification.- 3. Related work — Timing analysis.- 4. Related work — Performance analysis.- 5. MTG classification.- 6. MTG separation analysis.- 7. MTG latency and response time analysis.- 8. MTG rate analysis.- 9. MTG boundedness analysis.- 10. Summary.- 5. System Synthesis Methodology.- 1. Methodology overview.- 2. MTG model extraction.- 3. Resource estimation.- 4. Task concurrency management — Thread frame clustering.- 5. Task concurrency management — Thread frame scheduling.- 6. Task concurrency management — Execution model selection.- 7. RTOS synthesis.- 8. Summary.- 6. Conclusions.- 1. Motivation.- 2. Contributions.- 3. Future work.- Appendices.- Definitions.- 1. Multi-sets.- 2. MTG definitions and properties.- 2.1 Definitions.- 2.2 Behavioral and structural properties.- 3. Algebras.- 3.1 Number algebras.- 4. Relations and partial orders.- 4.1 Binary relations.- 4.2 Partial orders.- 5. Automata.

Date de parution :

Ouvrage de 438 p.

16x24 cm

Disponible chez l'éditeur (délai d'approvisionnement : 15 jours).

158,24 €

Ajouter au panier