Lavoisier S.A.S.
14 rue de Provigny
94236 Cachan cedex
FRANCE

Heures d'ouverture 08h30-12h30/13h30-17h30
Tél.: +33 (0)1 47 40 67 00
Fax: +33 (0)1 47 40 67 02


Url canonique : www.lavoisier.fr/livre/autre/integrated-circuit-packaging-assembly-and-interconnections/descriptif_1271775
Url courte ou permalien : www.lavoisier.fr/livre/notice.asp?ouvrage=1271775

Integrated Circuit Packaging, Assembly and Interconnections, Softcover reprint of hardcover 1st ed. 2007

Langue : Anglais
Couverture de l’ouvrage Integrated Circuit Packaging, Assembly and Interconnections

Reviewing the various IC packaging, assembly, and interconnection technologies, this professional guide and reference provides an overview of the materials and the processes, as well as the trends and available options, that encompass electronic manufacturing. It covers both the technical issues and touches on some of the reliability concerns with the various technologies applicable to packaging and assembly of the IC.

The focus is on the electronic manufacturing process, which in its simplest form involves assembly of the IC into a package or interconnect substrate or board. The book discusses the various packaging approaches available, namely, single chip, multichip, and Chip On Board; the assembly options, chip & wire, tape automated bonding, and flip chip; and the essential high density package/substrate manufacturing technologies, thin film, thick film, cofired ceramic, and laminate printed wiring board (PWB) processes. Included also is a discussion of high density PWBs using build up/sequential processes.

Integrated Circuit Packaging, Assembly and Interconnections is an introduction, a review and an update of packaging technologies.

Electronic Manufacturing and the Integrated Circuit.- Integrated Circuit Manufacturing: A Technology Resource.- Packaging the IC—Single Chip Packaging.- The Chip Scale Package.- Multichip Packaging.- Known Good Die (KGD).- Packaging Options—Chip on Board.- Chip & Wire Assembly.- Tape Automated Bonding—TAB.- Flip Chip—The Bumping Processes.- Flip Chip Assembly.- HDI Substrate Manufacturing Technologies: Thin Film Technology.- HDI Substrate Manufacturing Technologies: Thick Film Technology.- HDI Substrate Manufacturing Technologies: Cofired Ceramic.- Substrate Manufacturing Technologies: Organic Packages and Interconnect Substrate.

About the Author

A graduate of Fordham University with a BS in Physics Bill has had extensive experience in Microelectronics covering semiconductor processing and assembly, Hybrid Circuits, and PWB fabrication and assembly. He began his career with RCA Semiconductor Division and subsequently worked for General Electric and Lockheed Electronics. While at RCA he was awarded six U.S. patents covering wafer processing and semiconductor assembly. At General Electric he was a staff engineer and consultant for hybrid circuits and PWB manufacturing.

As Manager of Advanced Development at Lockheed, he was directly responsible for the design, construction, and operation of a state of the art Microelectronic Packaging facility supporting research, development, and manufacture of advanced hybrid circuits and multichip modules.

He became an independent consultant in 1988. His clients have included material suppliers, assembly equipment manufacturers, and component manufacturers.

His consulting activities has included work at NASA Headquarters in Washington D.C. where he provided technical expertise and assistance in developing an Advanced Integrated Circuit Packaging and Assembly Program.

Bill specializes in packaging and assembly, focusing on high density substrate manufacturing, and chip assembly including flip chip and chip scale packaging.

His company offers assistance in technology assessment and implementation, and specializes in technical audits of manufacturing operations directed towards yield improvement and reliability enhancement.

He has developed several educational and training courses which are offered at various national and international symposia and on-site presentations.

He is an active member of IMAPS where he is a Fellow of the Society and Past President of the Garden State Chapter.

 

 

Delivers the information designers need to implement the right packaging approach for their specific application Explains tradeoffs to be made at each level of packaging to form the most reliable product at the lowest cost Focuses on how package trends and assembly options are impacted by the IC and its mechanical, electrical, and thermal characteristics Identifies the IC manufacturing process (Wafer Fab) as a technology resource for the manufacture of high density interconnects Highlights flip chip as the next generation first level interconnect A comprehensive glossary of terms is included Includes supplementary material: sn.pub/extras

Date de parution :

Ouvrage de 300 p.

15.5x23.5 cm

Disponible chez l'éditeur (délai d'approvisionnement : 15 jours).

118,31 €

Ajouter au panier

Date de parution :

Ouvrage de 300 p.

15.5x23.5 cm

Sous réserve de disponibilité chez l'éditeur.

Prix indicatif 105,49 €

Ajouter au panier