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High Performance Integer Arithmetic Circuit Design on FPGA, 1st ed. 2016 Architecture, Implementation and Design Automation Springer Series in Advanced Microelectronics Series, Vol. 51

Langue : Anglais
Couverture de l’ouvrage High Performance Integer Arithmetic Circuit Design on FPGA
This book describes the optimized implementations of several arithmetic datapath, controlpath and pseudorandom sequence generator circuits for realization of high performance arithmetic circuits targeted towards a specific family of the high-end Field Programmable Gate Arrays (FPGAs). It explores regular, modular, cascadable and bit-sliced architectures of these circuits, by directly instantiating the target FPGA-specific primitives in the HDL. Every proposed architecture is justified with detailed mathematical analyses. Simultaneously, constrained placement of the circuit building blocks is performed, by placing the logically related hardware primitives in close proximity to one another by supplying relevant placement constraints in the Xilinx proprietary ?User Constraints File?. The book covers the implementation of a GUI-based CAD tool named FlexiCore integrated with the Xilinx Integrated Software Environment (ISE) for design automation of platform-specific high-performance arithmetic circuits from user-level specifications. This tool has been used to implement the proposed circuits, as well as hardware implementations of integer arithmetic algorithms where several of the proposed circuits are used as building blocks. Implementation results demonstrate higher performance and superior operand-width scalability for the proposed circuits, with respect to implementations derived through other existing approaches. This book will prove useful to researchers, students and professionals engaged in the domain of FPGA circuit optimization and implementation.
Introduction.- Architecture of Target FPGA Platform.- A Fabric Component based Design Approach for High Performance Integer Arithmetic Circuits.- Architecture of Data path Circuits.- Architecture of Control path Circuits.- Compact FPGA Implementation of Linear Cellular Automata.- Design Automation and Case Studies.- Conclusions and Future Work.

Ayan Palchaudhuri is a Ph.D. student in the Department of Electronics and Electrical Communication Engineering (E&ECE) of Indian Institute of Technology (IIT) Kharagpur. He has received the M.S. degree from the Department of Computer Science and Engineering (CSE), IIT Kharagpur, in 2015. He has over two-and-a-half years of work experience as a Junior Project Assistant in the Department of CSE, IIT Kharagpur. His research interests include VLSI Architecture Design and Computer Arithmetic. He is the co-author of two conference papers, one journal, one book chapter and a patent has been filed based on his research work. His research work has been recognized with the Best Poster Award in the Student Research Symposium of the 21st IEEE International Conference on High Performance Computing (HiPC) 2014.

Rajat Subhra Chakraborty is Assistant Professor in the Computer Science and Engineering Department of Indian Institute of Technology Kharagpur. He has a Ph.D. in Computer Engineering from Case Western Reserve University (Ohio, U.S.A.) and a B.E. (Hons.) in Electronics and Telecommunication Engineering from Jadavpur University (India) in 2005. He has work experience at National Semiconductor and AMD. His research interests include: Hardware Security, VLSI Design and Design Automation and Reversible Watermarking for digital content protection. He is the co-author of two published books, four book chapters and over 50 publications in international journals and conferences of repute. He is one of the recipients of the "IBM Faculty Award" for 2012, and a "Royal Academy of Engineering (U.K.) Fellowship" in 2014. He holds 1 U.S. patent, and 2 more international patents and 3 Indian patents have been filed based on his research work. Dr. Chakraborty is a member of IEEE and ACM.

Describes the optimized implementations of several arithmetic data path, control path and pseudorandom sequence generator circuits

Proposed designs outperform and have superior operand-width scalability, compared to implementations based on native DSP hard macros provided by Xilinx or those derived by the traditional Behavioral HDL-to-implementation design flow

Proposes a unified framework to design and implement high performance integer arithmetic circuits using "fabric logic" available on the leading FPGA platforms from Xilinx

Provides detailed mathematical analysis aimed at deriving the proposed architectures step-by-step

Describes and implements Design automation of the proposed design methodology, which integrates easily into the standard (non-licensed) Xilinx ISE design environment

Includes supplementary material: sn.pub/extras

Date de parution :

Ouvrage de 114 p.

15.5x23.5 cm

Disponible chez l'éditeur (délai d'approvisionnement : 15 jours).

105,49 €

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