High Performance Computing Programming and Applications Chapman & Hall/CRC Computational Science Series

High Performance Computing: Programming and Applications presents techniques that address new performance issues in the programming of high performance computing (HPC) applications. Omitting tedious details, the book discusses hardware architecture concepts and programming techniques that are the most pertinent to application developers for achieving high performance. Even though the text concentrates on C and Fortran, the techniques described can be applied to other languages, such as C++ and Java.

Drawing on their experience with chips from AMD and systems, interconnects, and software from Cray Inc., the authors explore the problems that create bottlenecks in attaining good performance. They cover techniques that pertain to each of the three levels of parallelism:

• Message passing between the nodes
• Shared memory parallelism on the nodes or the multiple instruction, multiple data (MIMD) units on the accelerator
• Vectorization on the inner level

After discussing architectural and software challenges, the book outlines a strategy for porting and optimizing an existing application to a large massively parallel processor (MPP) system. With a look toward the future, it also introduces the use of general purpose graphics processing units (GPGPUs) for carrying out HPC computations. A companion website at www.hybridmulticoreoptimization.com contains all the examples from the book, along with updated timing results on the latest released processors.

Introduction. Multi-Core Architectures for the Applications Programmer. Compiling for Multi-Core Architectures. Programming for Cache-Based Architectures. Programming for DDE Instructions. Programming for Distributed Memory Clusters. Programming for Multi-Core Distributed Memory Clusters. Using OpenMP and Pthreads across the Cores within the Node. What the Programmer Needs to Do? Message Passing Issues. Performance Analysis. Application Analysis.

John Levesque works in the Chief Technology Office at Cray Inc., where he is responsible for application performance on Cray’s HPC systems. He is also director of Cray’s Supercomputing Center of Excellence at the Oak Ridge National Laboratory (ORNL). ORNL was the first site to install a Petaflop Cray XT5 system, Jaguar; as of June 2010, it is the fastest computer in the world according to the TOP500 list.
For the past 40 years, Mr. Levesque has optimized scientific application programs for successful HPC systems. He is an expert in application tuning and compiler analysis of scientific applications.

Gene Wagenbreth is a senior system programmer in the Information Sciences Institute at the University of Southern California, where he is applying GPGPU technology in sparse matrix solvers, image tomography, and real-time computational fluid dynamics. He also presents courses on the use and programming of GPUs.
Since the 1970s, Mr. Wagenbreth has worked with most of the highest performance computers, including Cray models, other vector processors, hypercubes, and clusters. He has worked with shared and distributed memory computers using MPI, OpenMP, pthreads, and other techniques. He has also applied parallel processing in numerous fields, including seismic analysis, reservoir simulation, weather forecasting, and battlefield simulations.