High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip, Softcover reprint of the original 1st ed. 2018 Computer Architecture and Design Methodologies Series
Introduction.- Background.- Related Work.- High-level Fault Injection and Simulation.- Architectural Reliability Estimation.- Architectural Reliability Exploration.- System-level Reliability Exploration.- Conclusion and Outlook.
Offers a systematic approach to high-level reliability estimation and exploration
Presents step-by-step procedures for 11 novel techniques and solutions
Includes more than 100 figures and illustrations
Includes supplementary material: sn.pub/extras
Date de parution : 05-2018
Ouvrage de 197 p.
15.5x23.5 cm
Date de parution : 07-2017
Ouvrage de 197 p.
15.5x23.5 cm
Thème de High-level Estimation and Exploration of Reliability for... :
Mots-clés :
Architectural Reliability Estimation; System- Level Reliability Exploration; Architectural Fault Tolerance; Processor Design; Asymmetric Reliability; System-Level Design; Probabilistic Error Masking Matrix (PeMM); Node Fault Tolerance (NFT); Reliability Task Mapping; Statistical Error Confinement