Hardware Protection through Obfuscation, Softcover reprint of the original 1st ed. 2017

Part 1: Hardware Obfuscation Preliminaries.- Introduction to Hardware Obfuscation: Motivation, Methods and Evaluation.- VLSI Test and Hardware Security Background for Hardware Obfuscation.- Part 2: Logic-based Hardware Obfuscation.- Logic Encryption.- Gate Camouflaging-based Obfuscation.- Permutation-Based Obfuscation.- Protection of Assets from Scan Chain Vulnerabilities through Obfuscation.- Part 3: Finite State Machine (FSM) Based Hardware Obfuscation.-Active Hardware Metering by Finite State Machine Obfuscation.- State Space Obfuscation and its Application in Hardware Intellectual Property Protection.- Structural Transformation-based Obfuscation.- Part 4: Hardware Obfuscation Based on Emerging Integration Approaches.- Part IV Hardware Obfuscation Based on Emerging Integration Approaches.- Split Manufacturing.- Obfuscated Built-in Self Authentication.- 3D/2.5D IC based Obfuscation.- Part 5: Other Hardware Obfuscation Building Blocks.- Obfuscation and Encryption for Securing Semiconductor Supply Chain.

Domenic Forte received his B.S. degree in Electrical Engineering from Manhattan College, Riverdale, NY, USA, in 2006, and the M.S. and Ph.D. degrees in Electrical Engineering from the University of Maryland, College Park, MD, USA, in 2010 and 2013, respectively. Currently, he is an Assistant Professor with the Electrical and Computer Engineering Department at University of Florida. His research is primarily focused on the domain of hardware security and includes investigation of hardware security primitives, hardware Trojan detection and prevention, security of the electronics supply chain, hardware obfuscation, and anti-reverse engineering. His work has been recognized through several best paper awards and nominations from venues such as International Symposium on Hardware Oriented Security and Trust (HOST), Design Automation Conference (DAC), and Adaptive Hardware Systems (AHS). He is a coauthor of the book “Counterfeit Integrated Circuits- Detection and Avoidance”. He is currently serving as an Associate Editor for the Journal of Hardware and Systems Security (HaSS) and was previously Guest Editor of the IEEE Computer Special Issue on “Supply Chain Security for Cyber-Infrastructure.” He is also serving on the organizing committees of HOST and AsianHOST as well as the technical program committees of various noteworthy conferences and workshops.

Swarup Bhunia received his B.E. (Hons.) from Jadavpur University, Kolkata, India, and the M.Tech. degree from the Indian Institute of Technology (IIT), Kharagpur. He received his Ph.D. from Purdue University, IN, USA, in 2005. Currently, Dr. Bhunia is a professor in the department of Electrical and Computer Engineering at University of Florida, Gainesville, FL, USA. Earlier, Dr. Bhunia has served as the T. and A. Schroeder associate professor of Electrical Engineering and Computer Science at Case Western Reserve University, Cleveland, OH, USA. He has over ten years of research and development exp