Design of High-Performance CMOS Voltage-Controlled Oscillators, 2003 The Springer International Series in Engineering and Computer Science Series, Vol. 708
Auteurs : Liang Dai , Harjani Ramesh
The digital switching noise coupled through the power supply and substrate is usually the dominant source of clock jitter. Improving the supply and substrate noise immunity of a PLL is a challenging job in hostile environments such as a microprocessor chip where millions of digital gates are present.
Date de parution : 10-2012
Ouvrage de 158 p.
15.5x23.5 cm
Disponible chez l'éditeur (délai d'approvisionnement : 15 jours).
Prix indicatif 158,24 €
Ajouter au panierDate de parution : 10-2002
Ouvrage de 158 p.
15.5x23.5 cm
Mots-clés :
CMOS; Phase; Potential; analog; analog circuit design; circuit; communication; microprocessor; model; modeling; simulation; tables